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data sheet ics814s208bkilf revision b october 13, 2011 1 ?2011 integrated device technology, inc. femtoclock ? crystal-to-lvds 8-output clock synthesizer ICS814S208I general description the ICS814S208I is an eight lvds output clock synthesizer designed for wireless infrastructure applications. the device generates eight copies of a se lectable 122.88mhz or 153.6mhz clock signal with excellent phase jitter performance. the pll is optimized for a reference frequency of 30.72mhz. both a crystal interface and a differential system clock input are supported for the reference frequency. an extra lvds output duplicates the reference frequency and is provided for clock tree cascading. the device uses idt?s third generation femtoclock? technology for an optimum of high clock frequency and low phase noise performance, combined with a low power consumption. a pll lock status output is provided for monitoring and diagnosis purpose. the device supports a 3.3v voltage supply and is packaged in a small, lead-free (rohs 6) 48-lead vfqfn package. the extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. features ? third generation femtoclock? technology ? selectable 122.88mhz or 153.6mhz output clock synthesized from a 30.72mhz fundamental mode crystal ? eight differential lvds clock outputs ? differential reference clock input pair ? pll lock indicator output ? crystal interface designed for a 30.72mhz, parallel resonant crystal ? rms phase jitter @ 122.88mhz , using a 30.72mhz crystal (12khz - 20mhz): 0.650ps (typical) ? rms phase jitter @ 153.6mhz, using a 30.72mhz crystal (12khz - 20mhz): 0.642ps (typical) ? lvcmos interface levels for the control input ? full 3.3v supply voltage ? available in lead-free (rohs 6) 48-lead vfqfn package ? -40c to 85c ambient operating temperature qlock qa nqa qb0 nqb0 qb1 nqb1 qb2 nqb2 qb3 nqb3 qb4 nqb4 qb5 nqb5 qb6 nqb6 qb7 nqb7 pulldown pulldown (2) pulldown pulldown pulldown pulldown pulldown osc noe_a xtal_in xtal_out ref_clk nref_clk ref_sel bw[1:0] bypass n_sel noe_b0 noe_b1 noe_b2 20 5, 4 pfd & lpf femtoclock? vco 570mhz - 640mhz pulldown pullup/ pulldown 0 1 2 1 0 20 pulldown f ref n block diagram
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 2 ?2011 integrated device technology, inc. pin assignment 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 gnd ref_sel bypass noe_b0 bw1 bw0 vdda gnd n_sel noe_b1 noe_b2 noe_a 36 35 34 33 32 31 30 29 28 27 26 25 vdd nqb7 qb7 nqb6 qb6 gnd vdd nqb5 qb5 nqb4 qb4 gnd gnd qb0 nqb0 qb1 nqb1 vdd gnd qb2 nqb2 qb3 nqb3 vdd xtal_in xtal_out vdd ref_clk nref_clk gnd vddol qlock gnd qa nqa vdd ICS814S208I 48-lead vfqfn 7.0mm x 7.0mm x 0.925mm, package body k package top view
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 3 ?2011 integrated device technology, inc. table 1. pin descriptions note: pulldown and pullup refer to internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1, 2 xtal_in, xtal_out input crystal oscillator interface. xtal_in is the input, xtal_out is the output. 3, 12, 18, 24, 30, 36 v dd power core power supply pins. 4 ref_clk input pulldown non-inverting differential reference clock input. differential output can accept the following differ ential input levels: lvpecl, lvds, cml. 5 nref_clk input pullup/ pulldown inverting differential reference clock inpu t. differential outp ut can accept the following differ ential input levels: lvpecl, lvds, cml. 6, 9, 13, 19, 25, 31, 41, 48 gnd power power supply ground. 7v ddol power output supply pin for the pll lock output (qlock). supports 3.3v, 2.5v or 1.8v. 8 qlock output pll lock indication. see table 3i for func tion. supports 3.3v, 2.5v or 1.8v. 10, 11 qa, nqa output differential clock output pa ir. lvds interface levels. 14, 15 qb0, nqb0 output differential clock output pair. lvds interface levels 16, 17 qb1, nqb1 output differential clock output pair. lvds interface levels 20, 21 qb2, nqb2 output differential clock output pair. lvds interface levels 22, 23 qb3, nqb3 output differential clock output pair. lvds interface levels 26, 27 qb4, nqb4 output differential clock output pair. lvds interface levels 28, 29 qb5, nqb5 output differential clock output pair. lvds interface levels 32, 33 qb6, nqb6 output differential clock output pair. lvds interface levels 34, 35 qb7, nqb7 output differential clock output pair. lvds interface levels 37 noe_a input pulldown output enable input. see table 3e for function. lvcmos/lvttl interface levels. 38, 39, 45 noe_b2, noe_b1, noe_b0 input pulldown output enable inputs. see tables 3f-3h for function. lvcmos/lvttl interface levels. 40 n_sel input pulldown frequency select pin. see table 3a for function. lvcmos/lvttl interface levels. 42 v dda power analog power supply. 43, 44 bw0, bw1 input pulldown pll bandwidth control pins. see table 3d for function. lvcmos/lvttl interface levels. 46 bypass input pulldown pll bypass mode select pin. see table 3b for function. lvcmos/lvttl interface levels. 47 ref_sel input pulldown reference select input. see table 3c for function. lvcmos/lvttl interface levels.
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 4 ?2011 integrated device technology, inc. table 2. pin characteristics function tables table 3a. output divider n function table note: n_sel is an asynchronous control. note: with f xtal = 30.72mhz and all control inputs in the default state, the ICS814S208I gener ates 30.72mhz at the qa output and 122.88mhz at the qbx outputs. table 3b. pll bypass function table note: bypass is an asynchronous control. note: in pll bypass mode, the frequency f ref is output at qa without freq uency division. ac specifications do not apply in pll bypass mode. table 3c. pll reference cl ock select function table note: ref_sel is an asynchronous control. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2pf r pulldown input pulldown resistor 51 k ? r pullup input pullup resistor 51 k ? r out output impedance qlock qlock = high, v ddol = 3.3v 26 ? qlock = high, v ddol = 2.5v 32 ? qlock = high, v ddol = 1.8v 44 ? qlock = low, v ddol = 3.3v, 2.5v, 1.8v 22 ? inputs operation n_sel n qb[0:7] frequency with f ref = 30.72mhz 0 (default) 5 122.88mhz, (4 * f ref ) 1 4 153.6mhz, (5 * f ref ) input operation bypass qa qb[0:7] 0 (default) f out, qa = f vco 20 f out, qbx = f ref * 20 n 1f out, qa = f ref (pll bypass) input operation ref_sel 0 (default) the crystal interface is selected as reference clock 1 the ref_clk input is selected as reference clock
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 5 ?2011 integrated device technology, inc. table 3d. pll bandwidth function table note: bw[1:0] is an asynchronous control. note: with the lowest pll bandwidth setting (bw[1:0] = 00, 240khz), the pll attenuates input reference jitter with spectral com ponents above 240khz. with the highest pll bandwidth setting (bw[1:0] = 11, 2mhz), the pll is not optimized for input reference jitter attenuation. table 3e. noe_a output enable function table note: noe_a is an asynchronous control. table 3i. qlock output function table note: qlock supports 3.3v, 2.5v or 1.8v according to the voltage supplied at v ddol . see table 4b. table 3f. noe_b0 output enable function table note: noe_b0 is an asynchronous control. table 3g. noe_b1 output enable function table note: noe_b1 is an asynchronous control. table 3h. noe_b2 output enable function table note: noe_b2 is an asynchronous control. inputs operation bw1 bw0 pll bandwidth 0 (default) 0 (default) 240khz 0 (default) 1 520khz 1 0 (default) 1mhz 112mhz input operation noea 0 (default) qa, nqa outputs are enabled 1 qa, nqa outputs are disabled (high-impedance) output pll status qlock 0 the pll is locked to the input reference clock 1 the pll is not locked to the input reference clock input operation noe_b0 0 (default) qb[0:3], nqb[ 0:3] outputs are enabled 1 qb[0:3]. nqb[0:3] outputs are disabled (high-impedance) input operation noe_b1 0 (default) qb[4:5], nqb[ 4:5] outputs are enabled 1 qb[4:5], nqb[4:5] outputs are disabled (high-impedance) input operation noe_b2 0 (default) qb[6:7], nqb[ 6:7] outputs are enabled 1 qb[6:7], nqb[6:7] outputs are disabled (high-impedance)
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 6 ?2011 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functio nal operation of product at t hese conditions or any conditions beyond those listed in the dc cha racteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply voltage, v dd 4.6v inputs, v i xtal_in other inputs 0v to v dd -0.5v to v dd + 0.5v outputs, v o (lvcmos) -0.5v to v dd + 0.5v outputs, i o (lvds) continuous current surge current 10ma 15ma package thermal impedance, ja 30.5c/w (0 mps) storage temperature, t stg -65 c to 150 c dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v5%, v ddol = 1.8v0.2v, 2.5v5% or 3.3v5%, t a = -40c to 85c note: for the power supply voltage sequence information application note, see page 12. item rating symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3v 3.465 v v dda analog supply voltage v dd ? 0.22 3.3v v dd v v ddol qlock output supply voltage 1.6 1.8 2.0 v 2.375 2.5 2.625 v 3.135 3.3 3.465 v i dda analog supply current 22 ma i dd power supply current 355 ma
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 7 ?2011 integrated device technology, inc. table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v5%, v ddol = 1.8v0.2v, 2.5v5% or 3.3v5%, t a = -40c to 85c table 4c. differential dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c note 1: common mode input voltage is defined as v ih . table 4d. lvds dc characteristics, v dd = 3.3v5%, t a = -40c to 85c table 5. crystal characteristics note 1: using typical crystal parameter for esr, c o , and c l in a 30.72mhz crystal. symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v dd = 3.3v 2.2 v dd + 0.3 v v il input low voltage v dd = 3.3v -0.3 0.8 v i ih input high current bw[1:0], bypass, noe_a, noe_b[2:0], ref_sel, n_sel v dd = v in = 3.465v 150 a i il input low current bw[1:0], bypass, noe_a, noe_b[2:0], ref_sel, n_sel v dd = 3.465v, v in = 0v -10 a v oh output high voltage qlock v ddol = 3.465v, i oh = -8ma 2.6 v v ddol = 2.625v, i oh = -8ma 1.8 v v ddol = 2v, i oh = -8ma 1.5 v v ol output low voltage qlock v ddol = 3.465v or 2.625v, i ol = 8ma 0.5 v v ddol = 2v, i ol = 8ma 0.4 v symbol parameter test conditio ns minimum typical maximum units i ih input high current ref_clk, nref_clk v dd = v in = 3.465v 150 a i il input low current ref_clk v dd = 3.465v, v in = 0v -10 a nref_clk v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage 0.15 1.0 v v cmr common mode input voltage; note 1 gnd + 1.2 v dd v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.375 v ? v os v os magnitude change 50 mv parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 28.5 30.72 32 mhz equivalent series resistance (esr) 80 ? shunt capacitance 7pf drive level; note 1 100 w
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 8 ?2011 integrated device technology, inc. ac electrical characteristics table 6. ac characteristics, v dd = 3.3v5%, v ddol = 1.8v0.2v, 2.5v5% or 3.3v5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: characterized using rohde & schwarz sma100a signal generator with f ref = 30.72mhz, unless noted otherwise. v dd and v dda connected. bw[1:0] = 00. note 1: refer to the phase noise plots. note 2: measured from the differential input crossi ng point to the differential output crossing point. note 3: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the output diffe rential cross points. note 4: this parameter is defined in accordance with jedec standard 65. note 5: defined as skew within a bank of outputs at the same voltage and with equal load conditions. symbol parameter test conditio ns minimum typical maximum units f vco vco frequency bypass = 0 570 614.4 640 mhz f out output frequency qb[0:7], nqb[0:7] n_sel = 0 114 122.88 128 mhz n_sel = 1 142.5 153.6 160 mhz qa, nqa bypass = 0 28.5 30.72 32 mhz f ref reference frequency byp ass = 0 28.5 30.72 32 mhz t jit(?) rms phase jitter (random); note 1 122.88mhz, integration range: 1khz ? 40mhz 0.695 0.96 ps 122.88mhz, integration range: 12khz ? 20mhz 0.650 0.89 ps 153.6mhz, integration range: 1khz ? 40mhz 0.714 0.93 ps 153.6mhz, integration range: 12khz ? 20mhz 0.642 0.89 ps n single-side band noise power 122.88mhz, offset: 100hz -91 dbc/hz 122.88mhz, offset: 1khz -118 dbc/hz 122.88mhz, offset: 10khz -130 dbc/hz 122.88mhz, offset: 100khz -128 dbc/hz t jit(per) period jitter, rms qa, nqa 2.1 4.0 ps qbx, nqbx 2.3 4.8 ps qbx, nqbx at 1 22.88mhz 2.3 4.0 ps tie time interval error accumulated period jitter, 10 6 samples 9 30 ps t pd propagation delay; note 2 ref_clk, nref_clk to qa, nqa, bypass = 1, ref_sel = 1 550 770 950 ps tsk(o) output skew; note 3, 4 bypass = 0 25 100 ps tsk(b) bank skew; note 4, 5 25 100 ps t r / t f output rise/fall time 10% to 90% 75 200 350 ps t lock pll lock time 20 100 ms odc output duty cycle qa, nqa bypass = 0 49 50 51 % qbx, nqbx bypass = 0 49 50 51 %
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 9 ?2011 integrated device technology, inc. typical phase noise at 122.88mhz typical phase noise at 153.6mhz 122.88mhz rms phase jitter (random) 12khz to 20mhz = 0.650ps (typical) noise power dbc hz offset frequency (hz) 153.6mhz rms phase jitter (random) 12khz to 20mhz = 0.642ps (typical) noise power dbc hz offset frequency (hz)
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 10 ?2011 integrated device technology, inc. parameter measureme nt information 3.3v lvds output load ac test circuit bank skew period jitter, rms differential input level output skew rms phase jitter scope qx nqx 3.3v5% power supply +? float gnd v dd v dda qbx qby nqbx nqby t sk(b) v oh v re f v ol mean period (first edge after trigger) reference point (trigger edge) 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10 -7 )% of all measurements histogram v dd gnd nref_clk ref_clk v cmr cross points v pp nqa qa nqby qby t sk(o) offset frequency f 1 f 2 phase noise plot rms jitter = area under curve defined by the offset frequency markers noise power
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 11 ?2011 integrated device technology, inc. parameter measurement in formation, continued output rise and fall time propagation delay offset voltage setup output duty cycle/pulse width/period differential output voltage setup propagation delay time interval error 10% 90% 90% 10% t r t f v od nqa, nqbx qa, qbx t pd nqa qa nref_clk ref_clk out out lvds dc input ? ? ? v os / ? v os v dd nqa, nqbx qa, qbx t pw t period t pw t period odc = x 100% ? ? ? 100 out out lvds dc input v od / ? v od v dd time tie 0 tie 1 tie 2 tie n ideal clock edge positions tie: time interval error = min, mean and max of tie 0...n
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 12 ?2011 integrated device technology, inc. applications information wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benef its of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is re commended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications ar e characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels power supply voltage sequence information no power sequence restrictions apply if v dd and v dda are supplied by the same power plane and the recommended v dda filter is used (see figure 6). v ddol may be applied at any time before or after v dd and v dda are applied. if v dd and v dda are not supplied by the same power plane, v dda must be powered on before or at the same time v dd is applied. the v ddol supply voltage may be applied at any time.
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 13 ?2011 integrated device technology, inc. 3.3v lvpecl clock input interface the ref_clk/nref_clk accepts lvpecl, lvds, cml and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the ref_clk/nref_clk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of t he driver component to confirm the driver termination requirements. figure 2a. ref_clk/nref_clk input driven by an idt open collector cml driver figure 2c. ref_clk/nref_clk input driven by a 3.3v lvpecl driver figure 2e. ref_clk/nref_clk input driven by a 3.3v lvds driver figure 2b. ref_clk/nref_clk input driven by a built-in pullup cml driver figure 2d. ref_clk/nref_clk input driven by a 3.3v lvpecl driver with ac couple ref_clk nref_clk lvpecl input cml 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v r1 50 ? r2 50 ? r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v lvpecl ref_clk nref_clk lvpecl input 3.3v r3 1k r4 1k r1 1k r2 1k 3.3v zo = 50 ? zo = 50 ? 3.3v c1 c2 r5 100 lvds ref_clk nref_clk lvpecl input 3.3v r1 100 cml built-in pullup 3.3v zo = 50 ? zo = 50 ? ref_clk nref_clk lvpecl input r3 84 r4 84 r1 125 r2 125 r5 100 - 200 r6 100 - 200 3.3v lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v c1 c2 ref_clk nref_clk lvpecl input
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 14 ?2011 integrated device technology, inc. overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 3a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this c onfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 3b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 3a. general diagram for lvcmos driver to xtal input interface figure 3b. general diagram for lvpec l driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 15 ?2011 integrated device technology, inc. vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 4. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 16 ?2011 integrated device technology, inc. lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output struct ures: current source and voltage source. the standard termination schematic as shown in figure 5a can be used with either type of output structure. figure 5b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter comm on mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the out put structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lv d s driver lv d s driver lv d s receiver lv d s receiver z t c z o z t z o z t z t 2 z t 2 figure 5a. standard termination figure 5b. optional termination lvds termination recommendations for unused input and output pins i nputs: ref_clk/nref_clk inputs for applications not requiring the us e of the differential input, both ref_clk and nref_clk can be le ft floating. though not required, but for additional protection, a 1k ? resistor can be tied from ref_clk to ground. crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left float ing, we recommend that there is no trace attached. lvcmos output the unused lvcmos output can be left floating. there should be no trace attached.
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 17 ?2011 integrated device technology, inc. schematic example figure 6 shows an example of an ICS814S208I application schematic. in this example, the device is operated at a v dd = v ddol = 3.3v. the 12pf parallel resonant 30.72mhz crystal is used. the load capacitance values c1 = 6.8pf and c2 = 6.8pf are recommended for frequency accuracy. depending on the parasitics of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. crystals with other load capacitance specifications can be used. for this device, the crystal load capacitors are r equired for proper operation. as with any high speed analog circuitry, the power supply pins are vulnerable to noise. to achieve optimum jitter performance, power supply isolation is required. the ICS814S208I provides separate power supplies to isolate from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side of the pcb and the other components can be placed on the opposite side. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for wide range of noise frequencies. this low-pass filter starts to atte nuate noise at approximately 10khz. if a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. figure 6. ICS814S208I schematic example logic control input examples lvpecl driv er c14 0.1uf to logic input pins noe_b2 set logic input to '1' c5 0.1uf (u1:36) xta l _ i n vdd (u1:24) c3 0.1u nref_clk qa c15 0.1uf xtal_out c7 10uf c11 0.1uf r8 84 r7 84 c6 0.1uf set logic input to '0' vdd c9 0.1uf c12 0.1uf c13 0.1uf by pass zo_dif f = 100 ohm r9 50 r2 100 vdda + - qb7 bw0 vdd=3.3v x1 30.72mhz qlock blm18bb221sn1 ferrite bead 1 2 (u1:12) vdd c8 0.1uf (u1:30) vddol ru1 1k blm18bb221sn1 ferrite bead 1 2 + - (u1:18) c4 10u lvds termination rd2 1k r4 125 zo = 50 vdd u1 37 38 39 40 41 42 43 44 45 46 47 48 1 2 4 3 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 36 35 34 33 32 31 30 29 28 27 26 25 49 noe_a noe_b2 noe_b1 n_sel gnd vdda bw 0 bw 1 noe_b0 bypass ref_sel gnd xtal_in xtal_out ref_clk vdd nref_clk gnd vddol qlock gnd qa nqa vdd vdd nqb3 qb3 nqb2 qb2 gnd vdd nqb1 qb1 nqb0 qb0 gnd vdd nqb7 qb7 nqb6 qb6 gnd vdd nqb5 qb5 nqb4 qb4 gnd pad r5 2.2k nqa zo_dif f = 100 ohm noe_b1 c2 6.8pf nqa vdd c1 6.8pf to logic input pins ref_sel vdd bw1 vdd r6 50 (u1:7) r1 10 3.3v c16 0.1uf vdd r3 125 alternate lvds termination nqb7 n_sel noe_b0 vddol=3.3v c10 10uf vddol (u1:3) ref_clk 1 2 p f 3.3v qa ld1 ru2 not install rd1 not install noe_a zo = 50
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 18 ?2011 integrated device technology, inc. power considerations this section provides information on power dissipa tion and junction temperature for the ICS814S208I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics14s208i is the sum of the core power plus the analog power plus the power dissipation in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. the maximum current at 85c is as follows: i dd_max = 332ma i dda_max = 20ma power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (332ma + 20ma) = 1219.68mw 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and bon d pad, and directly affects the reliabilit y of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 30.5c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.220w * 30.5c/w = 122.2c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ja for 48 lead vfqfn, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 30.5c/w 26.7c/w 23.9c/w
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 19 ?2011 integrated device technology, inc. reliability information table 8. ja vs. air flow table for a 48-lead vfqfn transistor count the transistor count for ICS814S208I is: 9,137 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 30.5c/w 26.7c/w 23.9c/w
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 20 ?2011 integrated device technology, inc. package outline and package dimensions package outputline -k suffix for 48 lead vfqfn table 9. packagedimensions for 48 lead vfqfn reference document: id t drawing #psc-4203 n-1 n chamfer 1 2 n-1 1 2 n radius 4 4 bottom view w/type c id bottom view w/type a id there are 2 methods of indicating pin 1 corner at the back of the vfqfn package are: 1. type a: chamfer on the paddle (near pin 1) 2. type c: mouse bite on the paddle (near pin 1) all dimensions in millimeters symbol minimum nominal maximum n 48 a 0.8 0.9 a1 0 0.02 0.05 a3 0.2 ref. b 0.18 0.25 0.30 d & e 7.00 basic d1 & e1 5.50 basic d2 & e2 5.50 5.65 5.80 e 0.50 basic r 0.20~0.25 zd & ze 0.75 basic l 0.35 0.40 0.45
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 21 ?2011 integrated device technology, inc. ordering information table 10. ordering information table note: parts that are ordered with an ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 814s208bkilf ics814s208bil lead-free, 48-lead vfqfn tray -40 c to 85 c 814s208bkilft ics814s208bil lead-free, 48 -lead vfqfn 1000 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specif ications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer ics814s208bkilf revision b october 13, 2011 22 ?2011 integrated device technology, inc. revision history sheet rev table page description of change date b t6 8 16 ac characteristics table - added period jitter spec for qbx, nqbx outputs at 122.88mhz. updated lvds termination application note. 10/13/11
ICS814S208I data sheet femtoclock ? crystal-to-lvds 8-output clock synthesizer disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features a nd performance, is subject to change wit hout notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informati on contained herein is provided without re presentation or warranty of any kind, whether express or implied, in cluding, but not limited to, the suitability of idt?s products for any particular purpose, an im plied warranty of merchantabilit y, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property right s of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ris k, absent an express, written agreement by idt. integrated device technology, idt and the idt l ogo are registered trademarks of idt. ot her trademarks and service marks used he rein, including protected names, logos and designs, ar e the property of idt or their respective third party owners. copyright 2011. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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